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The Open Graphics Development Board
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OGD1

Additional details are available on the Traversal Technology Product Page.

OGD1 is a PCI based FPGA development board currently in development by the Open Graphics Project. With 256MiB on-board memory, high bandwidth, a Lattice XP10 semiconductor FPGA and also a Xilinx Spartan-3 XC3S4000 FPGA, the GPL based design is capable of significant computing applications. Though primarily designed as a development platform for 3D-rendering hardware, this board is expected to be of interest to engineers and scientists in both the commercial and academic markets.

Those who significantly assist with the development of the Open Graphics Project at this stage are expected to be offered a board, to encourage and support their development work. The pre-order price is $750, with discounts to encourage purchasing online. Volume discounts, developer subsidies as well as academic discounts are also planned.

As this board is under development, questions should be directed to the Open Graphics Mailing list or to Traversal Technology.

With OGD1 the Open Graphics Project is progressing towards its' goal of developing graphics cards with fully published specifications and open source drivers suitable for desktop computing and embedded systems. This is available as pre-order from Traversal Technology who also offer alternative licensing options.

Prototype Board with Connectors Shown


Image


Board Notes
For those looking at the board, you will notice:
1x S Video Connector (Middle Left)
2x DVI-I Connector (Top and bottom left)
1x 64-bit 66MHz PCI-X Edge Connector (base)
1x Power plug (Top middle right)
1x 100 Pin IDC Connector (right)

DVI Head 1 is connected to 330MHz analog and dual-link DVI.
DVI Head 2 is connected to TV/s-video and dual-link DVI. Source OGPN10

OGD1 components guide: see the other components populating the board.

While DVI is quickly replacing the VGA connectors common today, you can readily convert from a DVI-I output to a standard 15-pin VGA with a small adaptor which currently costs around $6US.

Currently the interfaces to the chips on this board are being stress tested. This includes PCI, memory, ROM, and video.

Those purchasing this board from Traversal, the company founded by members of the Open Graphics Project, are expected to be provided with a library of reference logic for use in their designs, including controllers for memory, PCI, video, and SPI. The Spartan can be programmed via JTAG Header or over PCI bus with code compiled using tools provided by Xilinx free of cost. The XP10 comes preloaded with logic code for PCI which is currently under development.



Qualifying for the Open Graphics Project Developer Discounts


by R. Heasman: We want, at the very least:

  1. HDL code
  2. Drivers for Linux
  3. BIOS code
  4. Layout/Schematic design
  5. Documentation for all of the above
  6. Documentation for users to this was added
  7. HDL code to stress-test OGD1 boards
  8. Software code to stress-test any OGP/Traversal product and
  9. Documentation for all of the above
  10. Documentation for users
  11. Translations in other languages (it was agreed that an automated translation could potentially be much worse than no translation at all). Source:OGPN1

It is planned that Developers in need may also request further assistance from the Open Hardware Foundation?. This will also enable the community who wish to make donations, assist proven OGP Developers with purchasing the OGP Developer Discount Development boards. More will be announced as details become firm. Source OGPN8


Performance

The 2 dual-link DVI-I can each support resolutions up to 2560x1600, and the analogue output can reach a theoretical limit of 2048x1536 at 60 Hz. While the actual performance that will be reached cannot be predicted at this stage, our target for the OGD1 development board is similar to a Radeon 7000 Source OGPN18. OGD1 is not sold as an end user board as it is our development board for testing and development of code for the end user board called OGC.



Hardware Code Licenses

Source code to the reference logic is available under a variety of licenses, including the GNU General Public License. There are expected to be three licenses with certain OGA components (video, memory, PCI, SPI, etc.):
  1. Via GPL — you can use it on your own design, as long as you conform to GPL
  2. Single-use commercial — when you buy N OGA boards, you get N individual commercial licenses to use those IP blocks on this board however you want, regardless of the GPL.
  3. Full commercial — You pay a license fee and can use those blocks anywhere in any design, without concern for the GPL.

Given these term, we're planning on explicitly permitting someone to reprogram only the 4000, leaving the PCI controller intact and reselling it commercially... because effectively, they're reselling OGD1 boards as another product and conforming to the single-use commercial license for the IP that comes with it. Note that some of this ("Logic Core") won't come with OGD1 right away. But it doesn't matter where you get the code from (as long as it's Traversal's version); you can use it with OGD1 without restriction. Source OGPN15

Driver License

Drivers are expected to be licensed under the X11 or MIT license.


Programming OGD1

Lattice Semiconductor's ispLEVER Starter is only supported for Windows XP and 2000 and does not yet support the XP10. http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter.cfm
The Starter version is not tested to work on wine. The Linux version of ispLEVER is only tested to work on Red Hat Enterprise v3. http://www.latticesemi.com/products/designsoftware/isplever/index.cfm?source=topnav&jsessionid=ba30d6ea98a8$3FD$3F$

Programming the XP10 device currently requires purchased versions of ispLEVER which you can find at their online store:
http://www.latticesemi.com/store/software.cfm

Linux cable driver, as mentioned in OGPN18

Xilinx Webpack. The only free web pack that supports the 3S4000 is 6.3i with the later service packs installed.
http://direct.xilinx.com/direct/webpack/63/WebPACK_63_fcfull_i.exe
(Requires login)

  • Development_Tools?

The JTAG cable is connected to the 6-pin header marked J4, J5, and J6 as follows

+ — Vref G — Gnd
I — TDI (test data in)
O — TDO (test data out)
S — TMS (test mode select)
C — TCK (test clock)

- Further images are available on the Traversal Technologies website
Populated Circuit Board
http://opengraphics.openhardwarefoundation.org/images/ogd1_showcase/ogd1_top_600.jpg (lower resolution)
http://opengraphics.openhardwarefoundation.org/images/ogd1_showcase/ogd1_showcase_720.jpg
By Howard and Lourens


The Open Graphics Project Internal Design for OGD1 as a Graphics Card



Board Artwork


As we are focussed upon completing OGD1 board testing, the artwork will be updated at a later date.

Individual Artwork Layers

Note:These do not show all the ground planes and are outdated.
http://www.traversaltech.com/ogd1_images/OGD1_Layer1.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer2.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer3.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer4.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer5.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer6.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer7.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer8.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer9.pdf
http://www.traversaltech.com/ogd1_images/OGD1_Layer10.pdf

Circuit Board Images

Note:These do not show the latest revision which includes a new header.
http://www.traversaltech.com/ogd1_images/ogd1_with_labels.jpg
OGD1 Thumbnail with Connectors Shown
OGD1 Board ViewOGD1 Thumbnail With Connectors Labelled
OGD1 with Connectors Labelled
- artwork designed by Terry Hancock.
- symbols layout designed by lucmars.


Artwork License:

The material provided here is Copyright (C) 2006, Traversal Technology. This intellectual property is provided under the protection of United States copyright law and the GNU General Public License. Use of this intellectual property is permitted under the rules of the GPL or by commercial license and payment of royalty. Source http://www.traversaltech.com/OGD1_index.html

Circuit Board Schematic Latest Revision.

http://www.traversaltech.com/doc/OGD1V2_RevA.pdf
You are welcome to help out and look for bugs (Note that the page numbers are not in ascending order.)


Schematic Licensing Details
  • The IP being licensed here refers to schematics, artwork, and other information necessary to reproduce the OGD1 blank printed circuit board. Additional IP that may be necessary for manufacturing a fully functional device (such as bit files and firmware) is not covered here.
  • Traversal retains copyright of this design and has the right to privately and publicly license it any way they see fit, as well as produce derivative works without restriction, license others to have similar rights, etc.
  • This design is being released to the community under the GPL license.
  • By default, Traversal reserves the right to adopt into their privately licensable IP any changes or modifications offered by the community to the OGP, Traversal, or an agent of either. All such changes will also be released under GPL immediately. Trademarks associated with Traversal Technology and the Open Graphics Project are barred from any other use of this IP.



Contributing Code

People should start by submitting patches/files(or link to them) to the list, and after a period of "test" receive write access if requested.

If someone has been a member for a while, then they should just ask, and we can give them access.
The general policy should be to deal with "disagreements" via `ifdef directives, `include's and such so that the end user can select the features they want. Convergence should be our general strategy. That doesn't mean people can't contribute wholly new ideas. You can't converge two totally different ways of characterizing a problem (e.g. state machine in Verilog like our memory controller vs. von Neumann programmable like our video controller). But we should strive to have a "main" version of something that adopts good ideas from other contributions. Meanwhile, we can have "auxiliary" projects that likewise adopt from related projects, and at some point, we may choose to redefine who is "main". Source OGPN16

Sub Projects

We'll have three kinds of projects:


  1. OGA-specific — these things are used ONLY for OGA, so the direction should be clear, and all changes will be percolated through people in charge.
  2. Completely unrelated — hobbyist projects that will not be used in OGA, at least not in the short term. Those projects will get SUGGESTIONS, but no strict controls.
  3. Components used by both — these include things like standard video, memory, and PCI controllers. They will be (carefully monitored). But if someone wants to fork one, that's cool too.

(...)Forking is always an okay thing, although for some things, we may request that people flesh it out really well before requesting space on the SVN server. We especially don't want to have a lot of forks. 2 or 3 major ones are okay. But beyond that, people will be asked to combine their ideas with an existing fork. Source OGPN16

Documenting Projects
A Technical Reference can be a good provision. It's a file with written explanation of how the product works, and the reasons for the less obvious design decisions. It often includes key design calculations. It's meant to help engineering technicians, test engineers, and design engineers who come along later and need to update the design and it amounts to a technical manual for the product.Source OGPN16

German: OGD1



Created by josephblack. Last Modification: Friday 24 of September, 2010 22:20:23 UTC by smalltux.