OGD1 components guide

Verilog and EDIF netlists for the OGD1 board can be found here.
The full schematic can be found here.

Components and connections

A) 2x DVI transmitters (pair A)

Silicon Image SiI1178CSU DVI - XMT 48Pin - TSSOP

• Datasheets were available but the provider has moved the link. These will be provided with the board.

Schematic: U1 - U4

B) 2x DVI transmitters (pair B)

Silicon Image SiI1178CSU DVI - XMT 48Pin - TSSOP
Schematic: U1 - U4

SiI1178 Pinout

C) 1x 330MHz triple - 10 bit DAC (behind)

Philips TDA8777HL/24/C1S 3x10 bit 48 pin LQFP48 Package
Schematic: U26

• http://www.nxp.com/#/pip/pip=[pip=TDA8777_4]|pp=[v=d,t=pip,i=TDA8777_4,fi=TDA8777_4,ps=0][0]|nxp TDA8777HL
• nxp datasheet for TDA8777
• mirror

TDA8777HL Pinout

Pin Names	Pin Numbers	Description
R0 - R9	39 - 48	10-Bit Red Channel Input (R9 is MSB)
G0 - G9	1 - 10	10-Bit Green Channel Input (G9 is MSB)
B0 - B9	14 - 23	10-Bit Blue Channel Input (B9 is MSB)
OUTR	34 (33)	Red Analog (Complementary) Output Current
OUTG	32 (31)	Green Analog (Complementary) Output Current
OUTB	28 (27)	Blue Analog (Complementary) Output Current
BLANK	11	Composite Video Blanking control input (active Low)
SYNC	12	Composite Video Sync control input (active Low)
CLK	24	Digital clock input
COMP	35	Compliance Voltage output
VREF	36	Reference Voltage input
RSET	37	Resistor to set full-scale range.
PSAVE	38	Power Save control input (active Low)
VSS	25, 26	Analog ground.
VDD	13, 29, 30	Analog power supply voltage.

D) 1x TV chip

Conexant CX25874 Quad - DAC/TV - Out 64 Pin QFP package. (datasheet) Note that later versions of this datasheet are not public at present. There is another datasheet that is similar.
Schematic: U6

• Howard Oct 07 The CX25874 is almost functionally identical to the CX25870 and CX25898 . You can download the spec for the CX25898 here
• : http://www.icbank.com/icbank_data/online_seminar/conexant_060517/Aquila24_DS_102759A.pdf
• :and the spec for the CX25870 here http://arm.cirrus.com/files/schematics/edb9307/3_DATASHEETS/cx25870.pdf
• If you look at the "internal Registers" section in the CX25898 document, the differences with the CX25874 chip are shaded. Comparing the two specs, I can tell you that the differences are inconsequential.
• Oct 07 it was noticed that CX25874 does not appear the product line card anymore. This is not expected to be a concern as Howard has noted: (We) looked at a couple of chip brokers inventory lists (...) I don't think these will be a problem.

CX25874 Pinout


Guide to Pins

Pin Names	Pin Numbers	Description
XTL_BFO	1	Buffered crystal clock output.
P[0] - P[11]	2-8,13-17	Pixel inputs.
VSS	9,22,31	Digital ground for core logic (tie to same plane).
VDD	10,32	Digital power for core logic.
VDDO	11,36	Digital Input/Output power.
VSSO	12,34	Digital Input/Output ground.
HSYNC*	18	Horizontal sync input/output. TTL compatible.
VSYNC*	19	Vertical sync input/output. TTL compatible.
FIELD	20	Field control output. TTL compatible.
BLANK*	21	Digital composite blanking control. TTL compatible.
NC	23,33	No-connection.
VDDHV	25	Digital high-voltage supply for internal pads.
SLEEP	26	TTL compatible power-down control input.
RESET*	27	Reset control input. TTL compatible.
GPO[0] - GPO[2]	28-30	General-purpose output pins.
CLKI	35	Pixel clock input. TTL compatible.
CLKO	37	Pixel clock output. TTL compatible.
VDD_SIO	38	Serial interface supply pin. 1.1 V to 3.3 V.
SID	39	Serial interface data input/output. TTL compatible.
SIC	40	Serial interface clock input. TTL compatible.
ALTADDR	41	Alternate slave address input. TTL compatible.
VSS_SO	42	Serial interface ground.
PLL_COMP (or VDD_PLL)	43	PLL compensation pin. Use 1.0 µF cap to ground for decoupling.
VSS_PLL	44	PLL ground pin.
VSS_OSC	45	Crystal oscillator ground pin.
XTALIN	46	13.5000 MHz crystal input.
XTALOUT	47	13.5000 MHz crystal output. (I.e. connect between 46/47).
VAA_OSC	48	Crystal oscillator supply pin.
REG_IN (or VDD1)	49	Pass transistor emitter voltage.
REG_OUT	50	Pass transistor base voltage.
VSS_BG	51	Video DAC bandgap ground.
VAA_BG	52	Video DAC bandgap power.
VREF	53	Voltage reference pin. Use 1.0 µF cap to ground for decoupling.
FSADJUST	54	Full-scale adjust control pin. 402 Ohm (+1%) resistor to ground sets full scale.
COMP	55	Compensation pin. Use 1.0 µF cap to VAA (not ground).
NG_DAC	56	Analog circuit ground.
VAA_DAC	57,58	DAC Analog power.
DACA-DACD	60-62,59	DAC Analog outputs. Use 75 Ohm resistor to ground. Leave no connect if unused.
VSS_DAC	63,64	Common DAC Analog ground pins.

E) 2x4 256 Mbit DDR SDRAM 16Mx16 chips (front, behind) 66 Pin TSOP II package.

Samsung K4H561638H (datasheet, Verilog, mirror)
Schematic: U7,U9,U11,U13,U19 - U22
There used to be links here to K4H561638F, which appears to have been obsolesced.

T. Miller (Jun 06): To configure the Verilog model for the particular chip we're using, I added this to the top of the k4h561638f_a2_0501.v file (from the old K4H561638F model):

`define M256
`define X16
`define SCC

There are some errors showing with Icarus apparently from lack of event control support.

SDRAM Pinout

Memory Pin Out List

T. Miller (Jun 06): We are driving pairs of 16 - bit DDR chips together as a unit, so it's basically like driving a single 32 - bit chip.
For each group of 8 data lines (DQ), there is:
A single data strobe (DQS) that is just a data clock and;
A single data mask (DM) that is a byte - enable for writes.

Each pair of chips has a single set of control lines (address, ras,
cas, we(wr), bank, pclock, and nclock).

(...) If anyone wants to help (with a pin out list), just post changes to the list. You can have openoffice split pieces of spreadsheet out in CSV format, which I can then paste into place, and if there are corrections, just explain them.

the signals must be grouped properly according to the memory chips on pages 7 and 8 of the schematic. Note the resistors on page 9 for the name changes from M to MEM for some pins.

F) 1x Main FPGA

Xilinx Spartan XC3s4000 (datasheet, mirror)
Xilinx FPGA XC3s4000 900P-FBFGA
Schematic: U10

Howard, Andy, and Timothy tested whether we would be able to fit an OGA - compliant design into a Lattice ECP2 - 50. Our determination is that the Xilinx 3S4000 is the only chip available within the next 6 months that will meet our needs.

Xilnx FPGA Chip Details

Some results of this change:

• 10 - bit triple - DAC fully connected
• Some extra user I/O signals
• Potentially wider local bus between the two FPGAs
• More versatility on the signal types for the user I/Os
• Increase in OGD1 parts cost
• Potential to populate 3S5000, if necessary
• ISE 6.3i to synthesize for the 3S4000 Source OGPN10
  • Xilinx is currently on ISE 9.2i — why use 6.3i?

G) 1x Secondary FPGA

Lattice XP10 (datasheet, mirror)
The Lattice XP10 non - volatile, reprogrammable FPGA (LFXP10e-5fn256c)is used for PCI communication.
Schematic: U12
The exact part number for synthesis is LFXP10C-5F256C.

Lattice FPGA Chip Details

H) 1x SPI PROM 8Mbit ODG1 U8

SS25VF010-20-4C-SAE
1Mb SPI Serial Flash.
Part number identifier: SST25VF010.
Datasheet PDF filename: (datasheet, brief, mirror)
8 Pin SOIC Package.
Schematic U15.
Pin Out Table

CE#	1	- -	8	Vdd
SO	2	- -	7	Hold
WP#	3	- -	6	SCK
Vss	4	- -	5	SPI

Chip Details

J) 1x SPI PROM 16Mbit

16Mb SPI Serial Flash
Part Number Identifier: SST25VF016B
Datasheet PDF Filename: (datasheet, mirror)
8 Pin SOIC Package.
Schematic U8
Pin Out Table

CE#	1	- -	8	Vdd
SO	2	- -	7	Hold
WP#	3	- -	6	SCK
Vss	4	- -	5	SPI

Chip Details

K) 3x 500MHz DACs (optional) since replaced by a 92 Pin Connector.

T. Miller Nov 5: K has been replaced by a single 92 - pin Hirose expansion connector. It provides power, ground, analog inputs from the nearby DVI - I connector, and 33 differential signal pairs (or 66 digital signals).

• Hirose Electric FX11LA - 92P - SV

Site www.hirose-connectors.com The Site Search apparently is not compliant with web standards and requires Internet Explorer 5 or greater. Fortunately it allows a second search box with a google search of the site.
Connector: Male. Two rows at 0.5mm pin spacing.
Current 0.3 Amp Max. Voltage 50V Max. Note: the datasheet is more accurate than a wiki page...

• http://www.hirose.co.jp/cataloge_hp/e57305045.pdf
• http://www.hirose-connectors.com/connectors/H205SeriesGaiyou.aspx?c1=FX11&c3=3

L) 1x 64 - bit 66MHz PCI - X edge connector

M) 2x DVI - I connectors

DVI Head 1 is connected to 330MHz analog (C) and dual - link DVI.
Molex 74320 - 9010 (drawing, spec)
Schematic J4 - J9

DVI Female Pins

Pin	Description	Pin	Description
1	TMDS Data 2- Digital red - (Link 1)	2	TMDS Data 2+ Digital red + (Link 1)
3	TMDS Data 2/4 shield	4	TMDS Data 4- Digital green - (Link 2)
5	TMDS Data 4+ Digital green + (Link 2)	6	DDC clock
7	DDC data	8	Analog vertical sync
9	TMDS Data 1- Digital green - (Link 1)	10	TMDS Data 1+ Digital green + (Link 1)
11	TMDS Data 1/3 shield	12	TMDS Data 3- Digital blue - (Link 2)
13	TMDS Data 3+ Digital blue + (Link 2)	14	+5V Power for monitor when in standby
15	Ground Return for pin 14 and analog sync	16	Hot plug detect
17	TMDS data 0- Digital blue - (Link 1) and digital sync	18	TMDS data 0+ Digital blue + (Link 1) and digital sync
19	TMDS data 0/5 shield	20	TMDS data 5- Digital red - (Link 2)
21	TMDS data 5+ Digital red + (Link 2)	22	TMDS clock shield
23	TMDS clock+ Digital clock + (Links 1 and 2)	24	TMDS clock- Digital clock - (Links 1 and 2)
C1	Analog red	C2	Analog green
C3	Analog blue	C4	Analog horizontal sync
C5	Analog ground Return for R, G and B signals

Sources
http://en.wikipedia.org/wiki/DVI
http://www.interfacebus.com/Design_Connector_Digital_Visual_Interface_DVI_Bus.html
http://www.ddwg.org/

N) 1x S - Video connector

4 Position S - Video Conector, A circular minature DIN connector.
Part Number AMP 750069-1
Website www.AMP.com or http://catalog.tycoelectronics.com
Search: 750069-1
filename: ENG_CAT_82212_0498_4_-1.pdf

S-Video Pins

Pin 1	GND	Ground (Y)
Pin 2	GND	Ground (C)
Pin 3	Y	Intensity (Luminance)
Pin 4	C	Colour (Chrominance)

source http://en.wikipedia.org/wiki/S-Video

O) 1x 100 - pin IDC expansion bus connector

IDC Connector

T. Miller (Jul 06): The connector is for user I/O. If someone else wanted to design a board that connected to that (directly or indirectly), that would be okay. Also, it's primarily not cost - effective for us to provide things on daughter boards for OGC. For OGD1, it depends on the needs. OGD1 has holes for a reinforcement bar that you can use to stiffen it, along with an extender board, if you need to.

April 07 Timothy: Its (holes are for) a 3M part no. P50E - 100P1 - SR1 - EA. $5 to $10 from Newark Electronics depending on quantity. The dual row pin strip mentioned in the forwarded e - mail wont work because of the staggered pin layout. Single row strip (up to 25 pins) works but you cant get them to fit in adjacent rows, so you can only connect to 50
of the I/O. Source OGPN22

Website: www.3M.com
3M describe the male part number as P50E - XXXP1 - XX. XXXS refers to the number of contacts; 100P1 - SR1 refers to the 100 pins with Right Angle Tails. XX is the contact coating. EA = 10 μ" .25 μm gold with gold flash U slot. There are two rows of pins, One row is odd numbered, the other, even. Pitch Spacing:0.05''.

• http://multimedia.mmm.com/mws/mediawebserver.dyn?6666660Zjcf6lVs6EVs666N03COrrrrQ-

Available from Newark.com.

Other Components

Header 2 Pin (x6)

Schematic J4 - J9.

Header 3 Pin

Schematic J10

Single bit bus switch

SOTiny (PI5C3302)
(Replaced by?)
TI SN74CBT1G125DBVR (datasheet, mirror)
Schematic: U14 (p1)



Acts as a voltage-controlled switch, when OE is low, A and B are connected.

Power MOSFET

International Rectifier IRF7459 (datasheet)
Schematic: Q2 - Q7

IRF7459 Pinout

Pin	Description
1-3	Source
4	Gate
5-8	Drain

Quad 2-Input Or Gate

TI SN74ACT32D (datasheet)
Fairchild 74ACT32SC (datasheet)
mirror
Schematic: U27

7432 Pinout

PCI connector

German