OGD1_U12

Lattice XP10 in 256-Ball fpBGA ("Fine Pitch Ball Grid Array")

Lattice Part # LFXP10E-5FN256C

XP10 Pinout

Pre-assigned Contacts

Pin Names	Pins	Description
PROGRAMN	C2	?
CCLK	C1	Clock?
INITN	P3	Initialize?
DONE	C3	?
SLEEPN/TOE	P4	Sleep mode?
CFG0	C4	Configure?
CFG1	B4	Configure?
TCK	B14	?
TMS	C14	?
TDI	D14	?
TDO	E16	?
GND	A1, A16, F6, F11, G7 - G10, H5, H7 - H10, J7 - J10, J13, K7 - K10, L6, L11, T1, T16	Tie to Ground (Low).
VCC	D4, D13, E5, E12, M5, M12, N4, N13	Tie to Logic Power (High).
VCCIO0	F7, F8	Input/Output Power, 0
VCCIO1	F9, F10	Input/Output Power, 1
VCCIO2	G11, H11	Input/Output Power, 2
VCCIO3	J11, K11	Input/Output Power, 3
VCCIO4	L9, L10	Input/Output Power, 4
VCCIO5	L7, L8	Input/Output Power, 5
VCCIO6	J6, K6	Input/Output Power, 6
VCCIO7	G6, H6	Input/Output Power, 7
VCCJ	D16	?
VCCP0	H4	?
VCCP1	J12	?
VCCAUX	E4, E13, M4, M13	Auxillary Power (?)

(Hancock):
I'm still reading the datasheet to make sure I understand, but I believe the remaining pins (the light gray circles in the diagram above) are user-assignable. They do have some kind of designation system, though, which I need to document here.