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VCSTaskRegAccessLogic

Name

Design logic for the primary FPGA to process "engine" register accesses

Owner

You?

Status

Not yet started.

Description

Design logic for the primary FPGA to process "engine" register accesses (so we can configure the memory controller, video controller, etc.).

Notes

This is just another block of address decode.




Created by LourensVeen. Last Modification: Sunday 02 of December, 2007 17:29:31 UTC by LourensVeen.