Status

Here are the things we have:

• A PCI controller synthesizable for Xilinx
• A working memory controller
• A working video controller
• Pad rings that need to be cleaned up
• A synthesizable nanocontroller (HQ)
• An initial version of the PCI address decoder
• An initial version of the memory arbiter
• An initial version of the bridge

People

Here are the various people working on this. Join us and help out! Mailing Lists

Timothy Miller - lead designer, developer and visionary
Howard Parkin - bridging logic (Task 1.2)
Bruce Adcock - undeclared (20 hours)
Jim Dinan - undeclared
Farhan Mohamed Ali - memory arbiter (?)
Kenneth Østby - top-level modules (Task 1.6), bridging logic (Task 1.2)
Lourens Veen - keeping track of things, some documentation
Hamish - C, Asm, Testing/Troubleshooting
Petter Urkedal - HQ
Nick - Verilog coding
Andre Pouliot - Miscellaneous verilog coding

Tasks

Phase 1: Getting back to the demo with all Free HDL code

1. Modify the PCI controller so that it synthesizes for the secondary FPGA
2. Build the two halves of the bridge logic to carry memory/reg accesses between the FPGAs
3. Glue PCI to the bridge and the SPI PROM controller
4. Design logic for the primary FPGA to process "engine" register accesses
5. Design an arbiter that manages competing memory accesses between PCI and video.
6. Design top levels modules for both FPGAs and wrap with pad rings.

Phase 2: Installing HQ

1. Design I/O interfaces for HQ
2. Insert HQ into the secondary FPGA
3. Develop test code for HQ and run it

Phase 3: BIOS ROM

1. Get basic BIOS code together
2. Get started on VGA BIOS code

Phase 4: VGA

1. Complete the nanocode for HQ that emulates at least CGA 80x25 text mode
2. Complete the VGA BIOS code that sets up CGA text mode

Current Status

Below is a quick overview of the components. There are stages that
each component needs to go through before it's done. I'm going to
list the steps that have been verified completed. Let me know if I
should check off any more; there are pieces that have indeed been
through 5, but since mods have happened since then I hesitate.


Here are the stages:

(1) Design and code
(2) Unit sanity check (verify wiring, etc.)
(3) Unit simulation testing and debugging
(4) Unit synthesis for speed
(5) In-hardware test and debug
(6) Wire to other blocks with glue logic
(7) Chip-level sanity check
(8) Chip-level simulation and debug
(9) Chip-level synthesis
(10) Chip-level in-hardware test and debug


XP10 stuff:

PCI target — 1, 2, 3, 4, 6
PCI cfg space — 1, 2, 3, 4, 6
PCI addr decode — 1, 2, 3, 4, 6
SPI controller — 1, 2, 3, 4, 6
SPI wrapper — 1, 6
XP10 bridge — 1, 6
Bridge wrapper — 1, 6
S3 bootloader — 1, 2, 6
Clock gen — 1, 6
Misc XP10 glue — 1, 6
XP10 top level — 1, 6
Pin assignment — 0


3S4000 stuff:

Memory ctl — 1, 2, 3, 4, 6
Mem wrappers — 1, 6
Video ctl — 1, 2, 3, 4, 6
Vid wrapper — 1, 6
Bot vid output — 1
Top vid output — 1
S3 bridge — 1, 6
S3 addr decode — 1, 6
Arbiter — 1, 6
Clock gen — (stubbed)
Misc glue — 1, 6
S3 top level — 1, 6
Pin assignment — 0


Other:

Board-level sim — 1, 6
PCI master sim — 1, 2, 3, 6


For Phase II:

Microctl (HQ) — 1, 2, 3, 4
HQ wrapper — 0


Software:

VGA microcode — 0
x86 VGA BIOS — 0
X.org driver — needs trivial changes



NOTES:

As I continue to update this, I can add additional detail about units,
or we can post information to the wiki. In the mean time, here are a
few useful clarificaitons.

"Wrappers" typically entail particular kinds of glue logic that are
specific to the block in question. We design a module in a generic
way, then we use a wrapper to adapt it to specific needs. For
example, the "memory wrapper" (of which four are instantiated at the
top level) contains an arbiter, a memory controller (which is in fact
its own wrapper around other lower-level details), video address
counters, and data fifos. Indeed, the typical thing you'll find in a
wrapper is some kind of connecting fifo, particularly for cases where
the surrounding logic runs on one clock but the unit runs on a
different clock.

"Misc glue" typically overlaps heavily with "top level", as a
place-holder for any connective logic that I can't think of off the
top of my head. The a "top level" is a module that basically wires
together everything that goes into one chip.

The bootloader is logic in the XP10 that reads one of the SPI PROMs
and programs the 3S4000 in slave serial mode.

Pin assignments are done via config files. ".ucf" for the Xilinx. I
don't know what it's called for the Lattice. We actually have pin
assignments, but not enough to call it a "1".