This page covers building the FPGA and CPLD bitstreams for the OGD1 hardware


This is currently a rough draft of a work in progress. It will document the process for setting up and building the bitstream images for the two programmable chips on the OGD1 board. It will eventually also document the automation of that process so that we can do automated development and release builds.

More to come.

Initial setup

You need Subversion installed to pull a copy of the repository.

Get a fresh version of the repository. For the examples here I will use /data/scm/svn/ogp/ogp_build as the place where I store the copy of the repository.

cd /data/scm/svn/ogp/ogp_build
svn co svn://svn.opengraphics.org/ogp

You want to use a separate copy of the code base for the build so that in-progress changes in your workspace don't impact the build. You can follow these same steps for setting up builds of changes you make as well.

mcnamara@ecthelion:/data/scm/svn/ogp/ogp_build$ svn co svn://svn.opengraphics.org/ogp                                       
A    ogp/trunk                                                                                                              
A    ogp/trunk/schem                                                                                                        
A    ogp/trunk/schem/OGD1_Schematic.pdf                                                                                     
A    ogp/trunk/schem/OGD1_BOM.txt
A    ogp/trunk/ogsim/NEWS
A    ogp/trunk/ogsim/po
A    ogp/trunk/ogsim/po/Makefile.am
A    ogp/branches
A    ogp/tags     
Checked out revision 641.
mcnamara@ecthelion:/data/scm/svn/ogp/ogp_build$ ls -l
total 4
drwxr-xr-x 6 mcnamara users 4096 2009-11-05 20:27 ogp

Editing XP10 PLLs

There are two ways to update the PLL dividers. You can update the HDL, or you can edit the PLL settings after PAR. The former is obviously not required every time, but the latter will let you test different settings with having to re-route the entire device. As currently set, the bridge_clk PLL outputs 62.5MHz based on a 125MHz input. I know this is quite slow compared to the 80MHz target, but it is stable. Gotta make it work then we make it work fast. Using a 156.25MHz clock, set CLKI_DIV=5 and CLKFB_DIV=2. CLK_OP stays at 12.

To play around with the settings, fire up ispLEVER and start the IPexpress tool. Under Architecture_Modules? is PLL. Give it a temp file to save the generated code to and it will bring up a rather handy tool for figuring out what the valid dividers are. The current code takes its output from CLK_OP, not CLK_OK. You can get slightly more granular frequencies using CLK_OK, but not much. The XP10 PLLs are not nearly as flexible as the Xilinx ones.

Created by wpmcnamara. Last Modification: Tuesday 09 of November, 2010 23:34:54 UTC by wpmcnamara.